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sles088e ? august 2003 ? revised december 2004 tm features 2 30 w (btl) into 6 ? at 1 khz 95-db dynamic range (in system with tas5026) < 0.2% thd+n (in system ? 30 w rms into 6- ? resistive load) device power efficiency typical >90% into 6- ? load self-protection design (including undervoltage, overtemperature, and short conditions) with error reports internal gate drive supply voltage regulator emi compliant when used with recommended system design applications dvd receiver home theatre mini/micro component systems internet music appliance description the tas5122 is a high-performance, integrated stereo digital amplifier power stage designed to drive 6- ? speakers at up to 30 w per channel. the device incorporates ti?s purepath digital technology and is used with a digital audio pwm processor (tas50xx) and a simple, passive demodulation filter to deliver high-quality, high-efficiency, true-digital audio amplification. the efficiency of this digital amplifier is typically greater than 90%. overcurrent protection, overtemperature protection, and undervoltage protection are built into the tas5122, safeguarding the device and speakers against fault conditions that could damage the system. f ? frequency ? hz 20 100 1k 10k thd+n ? total harmonic distortion + noise ? % 0.01 0.1 1 20k r l = 6 ? t c = 75 c thd + noise vs frequency p o = 1 w p o = 10 w p o ? output power ? w 40m 100m 10 40 0.01 0.1 1 thd+n ? total harmonic distortion + noise ? % thd + noise vs output power r l = 6 ? t c = 75 c 1 p o = 30 w purepath digital and powerpad are trademarks of texas instruments. other trademarks are the property of their respective owners. please be aware that an important notice concerning availability , standard warranty, and use in critical applications of t exas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com copyright ? 2004, texas instruments incorporated
sles088e ? august 2003 ? revised december 2004 www.ti.com 2 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam duri ng storage or handling to prevent electrostatic damage to the mos gates. general information terminal assignment the tas5122 is offered in a thermally enhanced 56-pin dca package (thermal pad is on the bottom). output of the dca package is highly dependent on thermal design. see the thermal information section. therefore, it is important to design the heatsink carefully. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 gnd gnd greg dvdd gnd dgnd gnd pwm_ap pwm_am reset_ab pwm_bm pwm_bp dreg m1 m2 m3 d reg_rtn pwm_cp pwm_cm r eset_cd pwm_dm pwm_dp sd_ab sd_cd otw greg gnd gnd gnd gvdd bst_a pvdd_ a pvdd_ a out_a out_a gnd gnd out_b out_b pvdd_ b pvdd_ b bst_b bst_c pvdd_ c pvdd_ c out_c out_c gnd gnd out_d out_d pvdd_ d pvdd_ d bst_d gvdd gnd dca package (top view) absolute maximum ratings over o perating free-air temperature range unless otherwise noted (1) tas5122 units dvdd to dgnd ?0.3 v to 4.2 v gvdd to gnd 28 v pvdd_x to gnd (dc voltage) 28 v out_x to gnd (dc voltage) 28 v bst_x to gnd (dc voltage) 40 v greg to gnd (2 ) 14.2 v pwm_xp, reset , m1, m2, m3, sd , otw ?0.3 v to dvdd + 0.3 v maximum operating junction temperature, t j ?40 c to 150 c storage temperature ?40 c to 125 c (1) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. (2) greg is treated as an input when the greg pin is overdriven by gvdd of 12 v. ordering information t a package description 0 c to 70 c tas5122dca 56-pin small tssop package dissipation ratings package r jc ( c/w) r ja ( c/w) 56-pin dca tssop 1.14 see note 1 (1) the tas5122 package is thermally enhanced for conductive cooling using an exposed metal pad area. it is impractical to use the device with the pad exposed to ambient air as the only heat sinking of the device. for this reason, r ja , a system parameter that characterizes the thermal treatment, is provided in the application information section of the data sheet. an example and discussion of typical system r ja values are provided in the thermal information section. this example provides additional information regarding the power dissipation ratings. this example should be used as a reference to calculate the heat dissipation ratings for a specific application. ti application engineering provides technical support to design heatsinks if needed.
sles088e ? august 2003 ? revised december 2004 www.ti.com 3 terminal functions terminal function (1) description name no. function (1) description bst_a 54 p hs bootstrap supply (bst), external capacitor to out_a required bst_b 43 p hs bootstrap supply (bst), external capacitor to out_b required bst_c 42 p hs bootstrap supply (bst), external capacitor to out_c required bst_d 31 p hs bootstrap supply (bst), external capacitor to out_d required dgnd 6 p digital i/o reference ground dreg 13 p digital supply voltage regulator decoupling pin, capacitor connected to gnd dreg_rtn 17 p digital supply voltage regulator decoupling return pin dvdd 4 p i/o reference supply input (3.3 v) gnd 1, 2, 5, 7, 27, 28, 29, 36, 37, 48, 49, 56 p power ground (i/o reference ground ? pin 22) greg 3, 26 p gate drive voltage regulator decoupling pin, capacitor to gnd gvdd 30, 55 p voltage supply to on?chip gate drive and digital supply voltage regulators m1 14 i mode selection pin m2 15 i mode selection pin m3 16 i mode selection pin otw 25 o overtemperature warning output, open drain with internal pullup out_a 50, 51 o output, half-bridge a out_b 46, 47 o output, half-bridge b out_c 38, 39 o output, half-bridge c out_d 34, 35 o output, half-bridge d pvdd_a 52, 53 p power supply input for half-bridge a pvdd_b 44, 45 p power supply input for half-bridge b pvdd_c 40, 41 p power supply input for half-bridge c pvdd_d 32, 33 p power supply input for half-bridge d pwm_am 9 i input signal (negative), half-bridge a pwm_ap 8 i input signal (positive), half-bridge a pwm_bm 11 i input signal (negative), half-bridge b pwm_bp 12 i input signal (positive), half-bridge b pwm_cm 19 i input signal (negative), half-bridge c pwm_cp 18 i input signal (positive), half-bridge c pwm_dm 21 i input signal (negative), half-bridge d pwm_dp 22 i input signal (positive), half-bridge d reset_ab 10 i reset signal, active low reset_cd 20 i reset signal, active low sd_ab 23 o shutdown signal for half-bridges a and b sd_cd 24 o shutdown signal for half-bridges c and d (1) i = input, o = output, p = power
sles088e ? august 2003 ? revised december 2004 www.ti.com 4 functional block diagram greg gvdd greg dreg_rtn timing control gate drive pwm_ap out_a gnd pvdd_a bst_a greg protection a protection b reset greg otw sd dreg_rtn dreg greg ot protection uvp pwm receiver bst_b dreg to protection blocks gate drive timing control gate drive pwm_bp out_b gnd pvdd_b pwm receiver gate drive timing control gate drive pwm_cp out_c gnd pvdd_c bst_c greg protection c protection d reset greg pwm receiver bst_d gate drive timing control gate drive pwm_dp out_d gnd pvdd_d pwm receiver gate drive
sles088e ? august 2003 ? revised december 2004 www.ti.com 5 recommended operating conditions min typ max unit dvdd digital supply (1) relative to dgnd 3 3.3 3.6 v gvdd supply for internal gate drive and logic regulators relative to gnd 16 23 25.5 v pvdd_x half-bridge supply relative to gnd, r l = 6 ? to 8 ? 0 23 25.5 v t j junction temperature 0 125 c (1) it is recommended for dvdd to be connected to dreg via a 100- ? resistor. electrical characteristics pvdd_x = 23 v, gvdd = 23 v, dvdd = 3.3 v, dvdd connected to dreg via a 100- ? resistor, r l = 6 ? , 8x f s = 384 khz, unless otherwise noted. ac performance is recorded as a chipset with tas5010 as the pwm processor and tas5122 as the power stage. symbol parameter test conditions typical t a =25 c t a =25 c t case = 75 c units min/typ/ max ac performance, btl mode, 1 khz r l = 8 ? , unclipped, aes17 filter 24 w typ p o output power r l = 8 ? , thd = 10%, aes17 filter 29 w typ p o output power r l = 6 ? , thd = 0.4%, aes17 filter 30 w typ r l = 6 ? , thd = 10%, aes17 filter 37 w typ po = 1 w/ channel, r l = 6 ?, aes17 filter 0.05% typ thd+n total harmonic distortion + noise po = 10 w/channel, r l = 6 ?, aes17 filter 0.05% typ po = 30 w/channel, r l = 6 ?, aes17 filter 0.2% typ v n output rms noise a-weighted, mute, r l = 6 ? , 20 hz to 20 khz, aes17 filter 240 v max snr signal-to-noise ratio f = 1 khz, a-weighted, r l = 6 ? ,, aes17 filter 95 db typ dr dynamic range f = 1 khz, a-weighted, r l = 6 ? ,, aes17 filter 95 db typ internal voltage regulator dreg voltage regulator i o = 1 ma, pvdd = 18 v?30.5 v 3.1 v typ greg voltage regulator i o = 1.2 ma, pvdd = 18 v?30.5 v 13.4 v typ igvdd gvdd supply current, operating f s = 384 khz, no load, 50% duty cycle 24 (1) ma max idvdd dvdd supply current, operating f s = 384 khz, no load 1 5 ma max output stage mosfets r dson,ls forward on-resistance, ls t j = 25 c 155 m ? max r dson,hs forward on-resistance, hs t j = 25 c 155 m ? max (1) measured with ti standard manufacturing hardware configuration
sles088e ? august 2003 ? revised december 2004 www.ti.com 6 electrical characteristics pvdd_x = 23 v, gvdd = 23 v, dvdd = 3.3 v, r l = 6 ? , 8x f s = 384 khz, unless otherwise noted symbol parameter test conditions typical t a =25 c t a =25 c t case = 75 c units min/typ/ max input/output protection v uvp,g undervoltage protection limit, gvdd 7.4 6.9 v min v uvp,g undervoltage protection limit, gvdd 7.4 7.9 v max otw overtemperature warning 125 c typ ote overtemperature error 150 c typ oc overcurrent protection 5.0 a min static digital specification pwm_ap, pwm_bp, m1, m2, m3, sd , otw v ih high-level input voltage 2 v min v ih high-level input voltage dvdd v max v il low-level input voltage 0.8 v max leakage input leakage current ?10 a min leakage input leakage current 10 a max otw/shutdown (sd) internally pullup r from otw /sd to dvdd 30 22.5 k ? min v ol low-level output voltage i o = 4 ma 0.4 v max
sles088e ? august 2003 ? revised december 2004 www.ti.com 7 system configuration used for characterization (btl) pwm processor tas50xx tas5122 valid_1 42 41 4 13 11 10 9 8 7 gvdd out_c bst_d pvdd_c gnd pvdd_d pvdd_d pvdd_c out_d 52 53 55 out_d 54 gnd out_c 56 51 49 47 50 48 bst_c bst_b pvdd_b 44 46 43 45 6 14 15 16 12 5 1 2 3 10 h 10 h 470 nf 4.7 k ? 1000 f 100 nf pwm_ap_1 pwm_am_1 100 nf 100 nf 1.5 ? 100 nf 33 nf h-bridge power supply gate-drive power supply external power supply 4.7 k ? l pcb (2) dreg sd_cd m1 pwm_cm reset_cd pwm_dp sd_ab pwm_dm greg m2 m3 dreg_rtn pwm_cp otw gnd gnd gnd l pcb (2) 33 nf 100 nf 1.5 ? pvdd_b pvdd_a out_b gnd out_a gnd out_b gvdd out_a gnd pvdd_a bst_a 37 38 40 39 36 34 32 35 33 29 31 30 10 h 10 h 470 nf 4.7 k ? 1000 f 100 nf 100 nf 1.5 ? 100 nf 33 nf 4.7 k ? l pcb (2) l pcb (2) 33 nf 100 nf 1.5 ? 100 nf gnd pwm_bp gnd gnd pwm_ap reset_ab pwm_bm pwm_am greg dvdd gnd dgnd 25 23 22 21 20 19 18 26 27 28 24 17 1 f err_rcvy 100 nf valid_2 pwm_ap_2 pwm_am_2 100 ? 100 nf 1 f 1.5 ? 2 1.5 ? 1.5 ? (1) (1) (1) (1) (1) voltage clamp 30 v, pn smaj28a, mfg microsemi (2) l pcb : track in the pcb (1 mm wide and 50 mm long)
sles088e ? august 2003 ? revised december 2004 www.ti.com 8 f rom pwm processor figure 1. typical single-ended design with tas5122 dca
sles088e ? august 2003 ? revised december 2004 www.ti.com 9 typical characteristics figure 2 total harmonic distortion + noise vs output power p o ? output power ? w 500m 1 10 thd+n ? total harmonic distortion + noise ? % 0.01 0.1 10 50 r l = 6 ? t c = 75 c tas5122se 1 tas5122btl figure 3 total harmonic distortion + noise vs frequency f ? frequency ? hz 20 100 1k 10k thd+n ? total harmonic distortion + noise ? % 0.01 0.1 1 20k r l = 6 ? t c = 75 c p o = 1 w p o = 10 w p o = 30 w figure 4 f ? frequency ? khz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2 4 6 8 10121416182022 r l = 6 ? fft = ?60 db t c = 75 c tas5010 pwm processor device noise amplitude ? dbr ?60 dbfs fft figure 5 total harmonic distortion + noise vs output power p o ? output power ? w 40m 100m 10 40 0.01 0.1 1 thd+n ? total harmonic distortion + noise ? % r l = 6 ? t c = 75 c 1
sles088e ? august 2003 ? revised december 2004 www.ti.com 10 figure 6 vdd ? supply voltage ? v 0 5 10 15 20 25 30 35 40 45 50 55 0 2 4 6 8 101214161820222426 t c = 75 c p o ? output power ? w output power vs h-bridge voltage r l = 8 ? r l = 6 ? figure 7 p o ? output power ? w 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 f = 1 khz r l = 6 ? t c = 75 c ? system output stage efficiency ? % system output stage efficiency vs output power figure 8 p o ? output power ? w 0 1 2 3 4 5 0 5 10 15 20 25 30 f = 1 khz r l = 6 ? t c = 75 c p tot ? power loss ? w power loss vs output power figure 9 t c ? case temperature ? c 20 22 24 26 28 30 32 34 36 38 40 0 10 20 30 40 50 60 70 80 90 100 110 120 130 pvdd = 23 v r l = 6 ? p o ? output power ? w output power vs case temperature channel 2 channel 1
sles088e ? august 2003 ? revised december 2004 www.ti.com 11 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 f ? frequency ? hz amplitude ? dbr 10 100 1k 50k 10k figure 10 r l = 8 ? amplitude vs frequency r l = 6 ? figure 11 t j ? junction temperature ? c 120 130 140 150 160 170 180 190 200 0 102030405060708090100 r on ? on-state resistance ? m ? on-state resistance vs junction temperature
sles088e ? august 2003 ? revised december 2004 www.ti.com 12 theory of operation power supplies the power device only requires two supply voltages, gvdd and pvdd_x. gvdd is the gate drive supply for the device, regulated internally down to approximately 12 v, and decoupled with regards to board gnd on the greg pins through an external capacitor. greg powers both the low side and high side via a bootstrap step-up conversion. the bootstrap supply is charged after the first low-side turnon pulse. internal digital core voltage dreg is also derived from gvdd and regulated down by internal low-dropout regulators (ldrs) to 3.3 v. the gate-driver ldr can be bypassed for reducing idle loss in the device by shorting greg to gvdd and directly feeding in 12 v. this can be useful in an application where thermal conduction of heat from the device is difficult. bypassing the ldr reduces power dissipation. pvdd_x is the h-bridge power supply pin. two power pins exist for each half-bridge to handle the current density. it is important that the circuitry recommendations concerning the pvdd_x pins are followed carefully both topology- and layout-wise. for topology recommendations, see the system configuration used for characterization section. following these recommendations is important for parameters like emi, reliability, and performance. system power-up/power-down sequence powering up reset gvdd (1) pvdd_x (1) pwm_xp > 1 ms > 1 ms (1) pvdd should not be powered up before gvdd. during power up when reset is asserted low, all mosfets are turned off and the two internal half-bridges are in the high-impedance state (hi-z). the bootstrap capacitors supplying high-side gate drive are at this point not charged. to comply with the click and pop scheme and use of non-ti pwm processors, it is recommended to use a 4-k ? pulldown resistor on each pwm output node to ground. this precharges the bootstrap supply capacitors and discharges the output filter capacitor (see the system configuration used for characterization section) . after gvdd has been applied, it takes approximately 800 s to fully charge the bst capacitor. within this time, reset must be kept low. after approximately 1 ms, the power stage bootstrap capacitor is charged. reset can now be released if the modulator is powered up and streaming pwm signals to the power stage pwm_xp. a constant high dc level on pwm_xp is not permitted, because it would force the high-side mosfet on until it eventually ran out of bst capacitor energy and might damage the device. an unknown state of the pwm output signals from the processor is illegal and should be avoided, which in practice means that the pwm processor must be powered up and initialized before reset is deasserted high to the power stage. powering down for powering down the power stage, an opposite approach is necessary. reset must be asserted low before the valid pwm signal is removed. when ti pwm processors are used with ti power stages, the correct timing control of reset and pwm_xp is performed by the modulator. precaution the tas5122 must always start up in the high-impedance (hi-z) state. in this state, the bootstrap (bst) capacitor is precharged by a resistor on each pwm output node to ground. see system configuration used for characterization . this ensures that the power stage is ready for receiving pwm pulses, indicating either high- or low-side turnon after reset is deasserted to the power stage. with the following pulldown and bst capacitor size, the charge time is: c = 33 nf, r = 4.7 k ? r c 5 = 775.5 s after gvdd has been applied, it takes approximately 800 s to fully charge the bst capacitor. during this time, reset must be kept low. after approximately 1 ms, the power stage bst is charged and ready. reset can now be released if the pwm modulator is ready and is streaming valid pwm signals to the power stage. valid pwm signals are switching pwm signals with a frequency between 350?400 khz. a constant high level on the pwm_xp forces the high-side mosfet on until it eventually runs out of bst capacitor energy. putting the device in this condition should be avoided.
sles088e ? august 2003 ? revised december 2004 www.ti.com 13 in practice this means that the dvdd-to-pwm processor should be stable and initialization should be completed before reset is deasserted to the power stage. control i/o shutdown pin: sd the sd pin functions as an output pin and is intended for protection-mode signaling to, for example, a controller or other pwm processor device. the pin is open-drain with an internal pullup to dvdd. the logic output is, as shown in the following table, a combination of the device state and reset input: sd reset description 0 0 not used 0 1 device in protection mode, i.e., uvp and/or oc and/or ot error 1 (2) 0 device set high-impedance (hi-z), sd forced high 1 1 normal operation (2) sd is pulled high when reset is asserted low independent of chip state (i.e., protection mode). this is desirable to maintain compatibility with some ti pwm processors. temperature warning pin: otw the otw pin gives a temperature warning signal when temperature exceeds the set limit. the pin is of the open-drain type with an internal pullup to dvdd. otw description 0 junction temperature higher than 125 c 1 junction temperature lower than 125 c overall reporting the sd pin, together with the otw pin, gives chip state information as described in table 1. table 1. error signal decoding otw sd description 0 0 overtemperature error (ote) 0 1 overtemperature warning (otw) 1 0 overcurrent (oc) or undervoltage (uvp) error 1 1 normal operation, no errors/warnings chip protection the tas5122 protection function is implemented in a closed loop with, for example, a system controller or other ti pwm processor device. the tas5122 contains three individual systems protecting the device against fault conditions. all of the error events covered result in the output stage being set in a high-impedance state (hi-z) for maximum protection of the device and connected equipment. the device can be recovered by toggling reset low and then high, after all errors are cleared. overcurrent (oc) protection the device has individual forward current protection on both high-side and low-side power stage fets. the oc protection works only with the demodulation filter present at the output. see demodulation filter design in the application information section of this data sheet for design constraints. overtemperature (ot) protection a dual temperature protection system asserts a warning signal when the device junction temperature exceeds 125 c. the ot protection circuit is shared by all half-bridges. undervoltage (uv) protection undervoltage lockout occurs when gvdd is insufficient for proper device operation. the uv protection system protects the device under power-up and power-down situations. the uv protection circuits are shared by all half-bridges. reset functions the functions of the reset input are: reset is used for reenabling operation after a latching error event (pmode1). reset is used for disabling output stage switching (mute function). the error latch is cleared on the falling edge of reset and normal operation is resumed when reset goes high. protection mode autorecovery (ar) after errors (pmode0) in autorecovery mode (pmode0), the tas5122 is self-supported in handling of error situations. all protection systems are active, setting the output stage in the high-impedance state to protect the output stage and connected equipment. however, after a short time the device auto-recovers, i.e., operation is automatically resumed provided that the system is fully operational. the autorecovery timing is set by counting pwm input cycles, i.e., the timing is relative to the switching frequency. the ar system is common to both half-bridges. timing and function the function of the autorecovery circuit is as follows: 1. an error event occurs and sets the protection latch (output stage goes hi-z). 2. the counter is started.
sles088e ? august 2003 ? revised december 2004 www.ti.com 14 3. after n/2 cycles, the protection latch is cleared but the output stage remains hi-z (identical to pulling reset low). 4. after n cycles, operation is resumed (identical to pulling reset high) (n = 512). error protection latch shutdown autorecovery sd pwm counter a r-reset figure 12. autorecovery function latching shutdown on all errors (pmode1) in latching shutdown mode, all error situations result in a permanent shutdown (output stage hi-z). reenabling can be done by toggling the reset pin. all protection systems disabled (pmode2) in pmode2, all protection systems are disabled. this mode is purely intended for testing and characterization purposes and thus not recommended for normal device operation. mode pins selection the protection mode is selected by shorting m1/m2 to dreg or dgnd according to table 2. table 2. protection mode selection m1 m2 protection mode 0 0 reserved 0 1 latching shutdown on all errors (pmode1) 1 0 reserved 1 1 reserved the output configuration mode is selected by shorting the m3 pin to dreg or dgnd according to table 3. table 3. output mode selection m3 output mode 0 bridge-tied load output stage (btl) 1 reserved application information demodulation filter design and spike considerations the output square wave is susceptible to overshoots (voltage spikes). the spike characteristics depend on many elements, including silicon design and application design and layout. the device should be able to handle narrow spike pulses, less than 65 ns, up to 65 volts peak. for more detailed information, see ti application report slea025. the purepath digital amplifier outputs are driven by heavy-duty dmos transistors in an h-bridge configuration. these transistors are either off or fully on, which reduces the dmos transistor on-state resistance, r dson , and the power dissipated in the device, thereby increasing efficiency. the result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. it is recommended that a second-order lc filter be used to recover the audio signal. for this application, emi is considered important; therefore, the selected filter is the full-output type shown in figure 13. output a c1a tas51xx l output b l c1b c2 r (load) figure 13. demodulation filter (ad mode) the main purpose of the output filter is to attenuate the high-frequency switching component of the purepath digital amplifier while preserving the signals in the audio band. design of the demodulation filter affects the performance of the power amplifier significantly. as a result, to ensure proper operation of the overcurrent (oc) protection circuit and meet the device thd+n specifications, the selection of the inductors used in the output filter must be considered according to the following. the rule is that the inductance should remain stable within the range of peak current seen at maximum output power and deliver at least 5 h of inductance at 15 a. if this rule is observed, the tas5122 does not have distortion issues due to the output inductors, and overcurrent conditions do not occur due to inductor saturation in the output filter.
sles088e ? august 2003 ? revised december 2004 www.ti.com 15 another para meter to be considered is the idle current loss in the inductor. this can be measured or specified as inductor dissipation (d). the target specification for dissipation is less than 0.05. in general, 10- h inductors suffice for most applications. the frequency response of the amplifier is slightly altered by the change in output load resistance; however, unless tight control of frequency response is necessary (better than 0.5 db), it is not necessary to deviate from 10 h. the graph in figure 14 displays the inductance vs current characteristics of two inductors that are recommended for use with the tas5122. figure 14. inductance saturation i - current - a 4 5 6 7 8 9 10 11 0 5 10 15 l - inductance - h inductance vs current dfb1310a dasl983xx-1023 the selection of the capacitor that is placed across the output of each inductor (c2 in figure 13) is simple. to complete the output filter, use a 0.47- f capacitor with a voltage rating at least twice the voltage applied to the output stage (pvdd). this capacitor should be a good quality polyester dielectric such as a wima mks2-047ufd/100/10 or equivalent. in order to minimize the emi effect of unbalanced ripple loss in the inductors, 0.1- f, 50-v, smd capacitors (x7r or better) (c1a and c1b in figure 13) should be added from the output of each inductor to ground. thermal information r ja is a system thermal resistance from junction to ambient air. as such, it is a system parameter with roughly the following components: r jc (the thermal resistance from junction to case, or in this case the metal pad) thermal grease thermal resistance heatsink thermal resistance r jc has been provided in the package dissipation ratings section. the thermal grease thermal resistance can be calculated from the exposed pad area and the thermal grease manufacturer?s area thermal resistance (expressed in c-in 2 /w). the area thermal resistance of the example thermal grease with a 0.002-inch-thick layer is about 0.1 c-in 2 /w. the approximate exposed pad area is as follows: 56-pin htssop 0.045 in 2 dividing the example thermal grease area resistance by the surface area gives the actual resistance through the thermal grease for both ics inside the package: 56-pin htssop 2.27 c/w the thermal resistance of thermal pads is generally considerably higher than a thin thermal grease layer. thermal tape has an even higher thermal resistance. neither pads nor tape should be used with either of these two packages. a thin layer of thermal grease with careful clamping of the heatsink is recommended. it may be difficult to achieve a layer 0.001 inch thick or less, so the modeling below is done with a 0.002-inch-thick layer, which may be more representative of production thermal grease thickness. heatsink thermal resistance is generally predicted by the heatsink vendor, modeled using a continuous flow dynamics (cfd) model, or measured. thus, for a single monaural ic, the system r ja = r jc + thermal grease resistance + heatsink resistance. dca thermal information the thermally enhanced dca package is based on the 56-pin htssop, but includes a thermal pad (see figure 15) to provide an ef fective thermal contact between the ic and the pcb. the powerpad ? package (thermally enhanced htssop) combines fine-pitch, surface-mount technology with thermal performance comparable to much larger power packages. the powerpad package is designed to optimize the heat transfer to the pwb. because of the small size and limited mass of an htssop package, thermal enhancement is
sles088e ? august 2003 ? revised december 2004 www.ti.com 16 achieved by improving the thermal conduction paths that remove heat from the component. the thermal pad is formed using a patented lead-frame design and manufacturing technique to provide a direct connection to the heat-generating ic. when this pad is soldered or otherwise thermally coupled to an external heat dissipater, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. thermal methodology for the dca 56-pin, 2 15-w, 8- package the thermal design for the dca part (e.g., thermal pad soldered to the board) should be similar to the design in the following figures. the cooling approach is to conduct the dissipated heat into the via pads on the board, through the vias in the board, and into a heatsink (aluminum bar) (if necessary). figure 15 shows a recommended land pattern on the pcb. tas5122dca copper layer ? component side solder powerpad 4mm 8 mm 5 11 vias ( 0.3 mm) figure 15. recommended land pattern the lower via pad area, slightly larger than the ic pad itself, is exposed with a window in the solder resist on the bottom surface of the board. it is not coated with solder during the board construction to maintain a flat surface. in production, this can be accomplished with a peelable solder mask. an aluminum bar is used to keep the through-hole leads from shorting to the chassis. the thermal compound shown has a pad-to-aluminum bar thermal resistance of about 3.2 c/w. the chassis provides the only heatsink to air and is chosen as representative of a typical production cooling approach.
sles088e ? august 2003 ? revised december 2004 www.ti.com 17 ?? ?? 1 in. 0.1 in. thick sides of u-shaped chassis are 1.25 in. high (3.9 c/w) 56-pin dca package (1.14 c/w) insulating back panel insulating front panel stereo amplifier board wakefield type 126 thermal compound under via pads (3.2 c/w) wakefield type 126 thermal compound (0.1 c/w) 8-mm 10-mm 40-mm aluminum bar (0.09 c/w) 1 mm plastic top pcb (3.6 c/w) figure 16. 56-pin dca package cross-sectional view (side) ?? ?? ?? ?? ?? ?? . 1 in 0.1 in. thick sides of u-shaped chassis are 1.25 in. high (3.9 c/w) 8-mm 10-mm 40-mm aluminum bar (0.09 c/w) plastic top wakefield type 126 thermal compound (0.1 c/w) 56-pin dca package (1.14 c/w) (2 places) pcb (3.6 c/w) wakefield type 126 thermal compound under via pads (3.2 c/w) 4-40 machine screw with star washer and nut (3 places) stereo amplifier board figure 17. spatial separation with multiple packages the land pattern recommendation shown in figure 15 is for optimal performance with aluminum bar thermal resistance of 0.09 c/w. the following table shows the decrease in thermal resistance through the pcb with a corresponding increase in the land pattern size. use the table for thermal design tradeoffs.
sles088e ? august 2003 ? revised december 2004 www.ti.com 18 land pattern pcb thermal resistance 7 13 vias (5 10 mm) 2.2 c/w 5 11 vias (4 8 mm) 3.6 c/w thermal pad 8,20 mm 7,20 mm 3,90 mm 2,98 mm figure 18. thermal pad dimensions for dca package click and pop reduction ti modulators feature a pop and click reduction system that controls the timing when switching starts and stops. going from nonswitching to switching operation causes a spectral energy burst to occur within the audio bandwidth, which is heard in the speaker as an audible click, for instance, after having asserted reset lh during a system start-up. to make this system work properly, the following design rules must be followed when using the tas5122 power stage: the relative timing between the pwm_ap/m_x signals and their corresponding valid_x signal should not be skewed by inserting delays, because this increases the audible amplitude level of the click. the output stage must start switching from a fully discharged output filter capacitor. because the output stage prior to operation is in the high-impedance state, this is done by having a passive pulldown resistor on each speaker output to gnd (see system configuration used for characterization ). other things that can affect the audible click level: the spectrum of the click seems to follow the speaker impedance vs frequency curve?the higher the impedance, the higher the click energy. crossover filters used between woofer and tweeter in a speaker can have high impedance in the audio band, which should be avoided if possible. another way to look at it is that the speaker impulse response is a major contributor to how the click energy is shaped in the audio band and how audible the click is. the following mode transitions feature click and pop reduction in t exas instruments pwm processors. state click and pop reduced normal (1) mute yes mute normal (1) yes normal (1) error recovery (errcvy) yes error recovery normal (1) yes normal (1) hard reset no hard reset normal (1) yes (1) normal = switching references 1. tas5000 digital audio pwm processor data manual (slas270) 2. true digital audio amplifier tas5001 digital audio pwm processor data sheet (sles009) 3. true digital audio amplifier tas5010 digital audio pwm processor data sheet (slas328) 4. true digital audio amplifier tas5012 digital audio pwm processor data sheet (sles006) 5. tas5026 six-channel digital audio pwm processor data manual (sles041) 6. tas5036a six-channel digital audio pwm processor data manual (sles061) 7. tas3103 digital audio processor with 3d effects data manual (sles038) 8. digital audio measurements application report (slaa114) 9. system design considerations for true digital audio power amplifiers application report (slaa117)
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tas5122dca active htssop dca 56 35 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr TAS5122DCAG4 active htssop dca 56 35 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tas5122dcar active htssop dca 56 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tas5122dcarg4 active htssop dca 56 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 6-dec-2006 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. cu stomers should obtain the latest relevant information before placing orders and should verify that such info rmation is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and othe r quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by governm ent requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti component s. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implie d, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are us ed. information published by ti regarding third-party products or services does not consti tute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the pat ents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, lim itations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements diffe rent from or beyond the parameters stated by ti for that product or service voids all express and any imp lied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.c om audio www.ti.com/audio data converters dataconverter.ti.co m automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 6553 03 dallas, texas 75265 copyright ? 2007, texas instruments incorporated

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